EDA Tools:

1. DRC (Design Rule Checking):

A physical design process to determine if chip satisfies rules defined by the semiconductor manufacturer.

In electronics engineering, a design rule is a geometric constraint imposed on circuit board, semiconductor device, and integrated circuits(IC) designers to ensure their designs function properly, reliably, and can be produced with acceptable yield. Design rules for production are developed by process engineers based on the capability of their processes to realize design intent. Electronics design automation is used extensively to ensure that designers do not violate design rules; a process called design rule checking (DRC).

A design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to ensure that most of the parts work correctly.

The most basic design rules are shown in the diagram on the left. The first are single layer rules. A width rule specifies the minimum width of any shape in the design. A spacing rule specifies the minimum distance between two adjacent objects. These rules will exist for each layer of semiconductor manufacturing process, with the lowest layers having the smallest rules (typically 100 nm as of 2007) and the highest metal layers having larger rules (perhaps 400 nm as of 2007).

A two layer rule specifies a relationship that must exist between two layers. For example, an enclosure rule might specify that an object of one type, such as a contact or via, must be covered, with some additional margin, by a metal layer. A typical value as of 2007 might be about 10 nm.

The main objective of design rule checking (DRC) is to achieve a high overall yield and reliability for the design. DRC is a very computationally intense task. Usually DRC checks will be run on each sub-section of the ASIC to minimize the number of errors that are detected at the top level. If run on a single CPU, customers may have to wait up to a week to get the result of a Design Rule check for modern designs. Most design companies require DRC to run in less than a day to achieve reasonable cycle times since the DRC will likely be run several times prior to design completion. With today’s processing power, full-chip DRC’s may run in much shorter times as quick as one hour depending on the chip complexity and size.

Some example of DRC’s in IC design include:

  • Active to active spacing
  • Well to well spacing
  • Minimum channel length of the transistor
  • Minimum metal width
  • Metal to metal spacing
  • Metal fill density (for processes using CMP)
  • Poly density
  • ESD and I/O rules
  • Antenna effect

2. HDL Works:

HDL Works develops HDL (VHDL, Verilog, and mixed language) design tools for design entry, analysis and navigation. The current portfolio includes EASE (graphical design entry), HDL Companion (analysis and navigation) and Scriptum (HDL editing). These tools provide a substantial productivity improvement during the edit-compile-debug cycle.

EASE is a graphical design entry environment that includes a block diagram editor, state diagram editor, truth table editor, HDL sensitive text editor, version management, team based design, verification, linting, documentation generation in HTML format, IP integration and support for FPGA core generators, VHDL and Verilog support, and integrated interfaces to third party tools (simulators, synthesizers & place & route tools).

HDL Companion offers optimal exploration features to get all required design details of any HDL (VHDL and Verilog) design. HDL Companion analyses the HDL code and it provides the user easy access to the design details by offering features like signal tracing, link between use and definition, detailed view per design object, hierarchy view, etc.

IO checker is the bridge between FPGA and PCB design environments. It verifies if your FPGA is connected on the PCB using the same signals and pins as programmed in the FPGA tooling. Using intelligent matching an FPGA with over a 1000 pins can be verified in minutes. IO Checker verifies regular IOS, LVDS pairs and power & ground pins. FPGA constraints files can be created or updated.

Scriptum is is an HDL sensitive text editor that includes syntax coloring, column editing, line numbering, templates, identifier expansion, in- and outdenting, text-to-comment and vice-versa, lower-to-uppercase and vice-versa etc.



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